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·  Data rates: 2.5~32Gbps

·  Digital bus: 0.5~1Gbps

·  Multi-gear ratios

·  Reference clock: 100MHz

·  SSC: 0~-5000ppm

·  Termination: 100 Ohm differential

·  ESD:

   250V CDM,1000 Volt HBM(>1Gbps)

   500V CDM,2kV HBM(<1Gbps)

 

 

·  Vcc AC noise: < 30mVpp

·  Channel IL: up to 30dB

·  Return Loss: -10dB

·  DFx features for yield diagnosis

   & recovery

·  Analog monitors

·  PVT adaptation 

·  Channel equalization &

    adaptation

Features

SerDes IP 定制

Chip4Tao Technologies Inc provides the SerDes IP customization based on the advanced PMA core (PLL, CDR, EQ, HSIO) with support of the sophisticated digital design blocks (PCS, PIPE, Standard Protocol Controller). We have extensive design knowledge in wide range of technology nodes (3nm – 110nm) and various foundries like TSMC, SMIC etc.

·  Link rate

·  No. of Lanes

·  Reference clock frequency

·  Optional PCS, PIPE or application interface like AXI

·  Optional protocol controller like PCIe, SATA, MIPI CSI/DSI

·  Target foundries: SMIC, TSMC

·  Target technology nodes: 3nm - 110nm

 

 

 

Example Customization

Business Process

Spec & RFQ

 

 

Contract

Signing

 

PMA Tuning

Logic Design

 

Silicon Chaz

Deliverable Generation

Physical

Design

·  Integration guide

·  Verilog simulation model

·  Verilog testbench

·  Synthesis timing models

    in .lib and .db

·  Synthesis constraints

·  LEF file with pin sizes and locations

·  Scan chain model

·  GDSII

·  CDL Netlist

·  DRC report

·  Gate-level netlist and SDF

Front-End

Back-End

Deliverables

Overview